0000000000000000000000000000000000000000 5f71e002a55ced80d487c406b3bc8f23d964e5e2 Marc Feeley <feeley@iro.umontreal.ca> 1513272688 -0500	branch: Created from master
5f71e002a55ced80d487c406b3bc8f23d964e5e2 d2af2c08e9803f87bdab7259b04e1e19de556098 Marc Feeley <feeley@iro.umontreal.ca> 1513272843 -0500	commit: Add a CPU target to support X86 and ARM
d2af2c08e9803f87bdab7259b04e1e19de556098 1a41e9d513567ff8d3ceaa09adbfbbaef8897202 Marc Feeley <feeley@iro.umontreal.ca> 1517964506 -0500	pull: Fast-forward
1a41e9d513567ff8d3ceaa09adbfbbaef8897202 a454eba5d8ca0acfbef65319b52e29446706a51d Marc Feeley <feeley@iro.umontreal.ca> 1517968066 -0500	commit: x86 backend: reserve space for Scheme stack and avoid nul bytes at labels
a454eba5d8ca0acfbef65319b52e29446706a51d a17206b3a3f018c5f5894dc838b7a3b7c9ed6225 Marc Feeley <feeley@iro.umontreal.ca> 1517969804 -0500	cherry-pick: Add pushf and popf x86 instructions
a17206b3a3f018c5f5894dc838b7a3b7c9ed6225 724f36e5b184c2c8f51f8726edac5e09abad7ec6 Marc Feeley <feeley@iro.umontreal.ca> 1518028898 -0500	pull: Fast-forward
724f36e5b184c2c8f51f8726edac5e09abad7ec6 513b5baa5c949ae0aa5f59f275302a07b83c9521 Marc Feeley <feeley@iro.umontreal.ca> 1519241923 -0500	commit: Fix issue #333 (wrong assumption about sigset_t size)
513b5baa5c949ae0aa5f59f275302a07b83c9521 600e4034c993a29c636b9fbd266db51fd27a399a Marc Feeley <feeley@iro.umontreal.ca> 1519615844 -0500	pull: Merge made by the 'recursive' strategy.
